Constantly monitoring a status flag, a method known as polling, is inefficient because the processor is tied up waiting for an event instead of performing other tasks. A more powerful, event-driven approach is to use interrupts. An interrupt is a signal from hardware or software that demands immediate attention from the processor, allowing it to respond to events as they happen without constant monitoring.

10.1 Interrupt Fundamentals

• Hardware vs. Software Interrupts: Hardware interrupts are triggered by external devices, like a sensor or a timer overflowing. Software interrupts are triggered by a special instruction or an exceptional condition (like dividing by zero).
• Interrupt Service Routine (ISR): An ISR (or interrupt handler) is a special subroutine that the processor executes in response to an interrupt. You write the ISR to perform the action required by the event.
• Interrupt Vector Table: This is a fixed area in the 8051’s program memory (ROM) that stores the starting addresses for each ISR. When an interrupt occurs, the processor looks up the corresponding address in this table to find where to jump.

10.2 The 8051 Interrupts

The 8051 has six interrupt sources, each with a dedicated address (vector) in the Interrupt Vector Table.

10.3 Enabling and Prioritizing Interrupts

By default, all interrupts are disabled upon reset. They must be enabled in software before the processor will respond to them.

Interrupt Enable (IE) Register

The IE register is a bit-addressable register used to enable or disable individual interrupts. Each interrupt source has a corresponding bit in this register. However, the most critical bit is EA (Global Enable).

• EA (IE.7): This bit acts as a master switch. It must be set to 1 for any other interrupt to be recognized. If EA is 0, all interrupts are disabled, regardless of the state of the other bits in the IE register.

Interrupt Priority (IP) Register

The IP register allows you to assign one of two priority levels (high or low) to each interrupt. By default, all interrupts are at a low priority. If you set an interrupt’s corresponding bit in the IP register to 1, it is assigned a high priority. A high-priority interrupt can interrupt a low-priority interrupt service routine that is already in progress.

10.4 Interrupt Execution Flow

When a valid, enabled interrupt occurs, the processor performs the following sequence of actions:

1. It finishes executing the current instruction.
2. It saves the address of the next instruction (the contents of the Program Counter) on the stack.
3. It jumps to the corresponding address in the Interrupt Vector Table.
4. The ISR located at that address is executed.
5. The ISR must end with the RETI (Return from Interrupt) instruction. This instruction pops the saved address from the stack back into the Program Counter, allowing the main program to resume from where it was interrupted.

With an understanding of the 8051’s hardware and programming model, we can now turn to the tools that bring it all together.