2.0 Core Processing and Architecture
2.1 The Role of the Processor
The processor is the “heart of an embedded system,” responsible for taking inputs and producing outputs after processing data. A processor contains two essential units:
- Program Flow Control Unit (CU): Includes a fetch unit for retrieving instructions from memory.
- Execution Unit (EU): Contains circuits that implement instructions for data transfer, data conversion, and program control tasks like jumps and interrupts. It includes the Arithmetic and Logical Unit (ALU).
The processor operates on a continuous cycle of fetching and executing instructions in the sequence they are retrieved from memory.
2.2 Microprocessors vs. Microcontrollers
While both are central to embedded systems, microprocessors and microcontrollers have distinct differences. A microprocessor is a single VLSI chip containing a CPU, potentially with additional units like caches and floating-point processors. A microcontroller, also known as a microcomputer, is a single-chip VLSI unit that integrates a CPU with limited computational power but enhanced I/O capabilities and on-chip peripherals like RAM, ROM, and timers.
| Feature | Microprocessor | Microcontroller |
| Tasking | Multitasking in nature; can perform multiple tasks at a time. | Single-task oriented; designed for a specific task. |
| Components | RAM, ROM, I/O Ports, and Timers are added externally and can vary. | RAM, ROM, I/O Ports, and Timers are embedded on-chip and fixed in number. |
| Design | System design is heavier, costlier, and consumes more space and power. | System design is lightweight, cheaper, and consumes less power and space. |
| Flexibility | Designers can decide the number of memory or I/O ports needed. | The fixed number of components makes it ideal for limited, specific tasks. |
2.3 System Architectures: Von Neumann vs. Harvard
The architecture dictates how a system accesses memory for code and data. The 8051 microcontroller can support up to 128k of external memory (64k for program, 64k for data).
| Von Neumann Architecture | Harvard Architecture |
| A single shared memory and bus for both code and data. | Separate memories and signal buses for code and data. |
| The processor requires separate clock cycles to fetch code and then data. | A single clock cycle is sufficient as separate buses allow simultaneous access. |
| Slower in speed, requiring more time. | Higher speed, thus less time-consuming. (Source text has a contradiction here, this table reflects the bus access description) |
| Simple in design with a single sequential memory. | More complex in design. |
2.4 Instruction Set Architectures: CISC vs. RISC
Instruction set architecture determines the complexity and number of instructions a CPU can execute.
- CISC (Complex Instruction Set Computer): Can address a large number of instructions.
- RISC (Reduced Instruction Set Computer): Uses fewer instructions with simple constructs for faster execution within the CPU.
| Feature | CISC | RISC |
| Instruction Set | Larger set of instructions; easy to program. | Smaller set of instructions; difficult to program. |
| Compiler Design | Simpler compiler design. | Complex compiler design. |
| Addressing Modes | Many addressing modes, causing complex instruction formats. | Few addressing modes, fixed instruction format. |
| Execution Speed | Slower execution, as instructions must be read from memory and decoded. | Faster execution, as each instruction is executed by hardware. |
| Emphasis | Emphasis is on hardware. | Emphasis is on software. |
| Pipelining | Pipelining is not possible. | Pipelining of instructions is possible. |