2.0 The Core: Processors and Architectures
The processor is the heart of any embedded system, responsible for fetching and executing instructions. Understanding the different types of processors and the architectural models that govern their operation is fundamental to making informed design choices. This section will differentiate between microprocessors and microcontrollers and explore the key architectural designs that define how they access code and data.
2.1 Microprocessors vs. Microcontrollers
While often used interchangeably, these two types of processors serve different purposes in embedded design. A microprocessor is a single VLSI chip containing a CPU, often supplemented by caches and floating-point units for faster processing. A microcontroller, by contrast, is a complete computer on a single VLSI chip, integrating a CPU, RAM, ROM, I/O ports, timers, and other peripherals.
| Microprocessor | Microcontroller |
| Multitasking in nature; can perform multiple tasks simultaneously. | Single-task oriented; designed for a specific function like in a washing machine. |
| RAM, ROM, I/O ports, and timers are added externally. | RAM, ROM, I/O ports, and timers are embedded on the chip in fixed numbers. |
| Design is flexible; memory and I/O can be customized as needed. | Fixed number of components makes it ideal for a limited, specific task. |
| External components make the system larger, more expensive, and power-hungry. | Integrated components make the system lightweight, cheaper, and more power-efficient. |
2.2 Key Architectural Models
The way a processor accesses instructions and data is defined by its underlying architecture. The two primary models are Von Neumann and Harvard.
- Von Neumann Architecture: This model uses a single, shared bus for both instructions and data. Because the bus is shared, the processor needs to fetch code in a separate clock cycle and data in another clock cycle; it cannot perform these actions simultaneously. This simplifies the hardware design.
- Harvard Architecture: This model features separate storage and signal buses for instructions and data. This allows the CPU to access both simultaneously, significantly improving performance.
| Von Neumann Architecture | Harvard Architecture |
| Uses a single shared memory for code and data. | Uses separate memories for code and data. |
| Sequential access prevents simultaneous instruction and data fetch. | Separate buses allow simultaneous instruction and data fetch. |
| Slower speed due to shared bus. | Higher speed due to simultaneous access. |
| Simpler design. | More complex design. |
2.3 Instruction Set Architectures: CISC vs. RISC
The instructions a processor understands are defined by its instruction set architecture.
- Complex Instruction Set Computer (CISC): A CISC processor can address a large number of complex instructions. The emphasis is on hardware, where a single instruction can perform a multi-step operation.
- Reduced Instruction Set Computer (RISC): A RISC processor uses a smaller set of simpler instructions that execute much faster. The emphasis is on software, where complex operations are built by combining multiple simple instructions.
| CISC (Complex Instruction Set Computer) | RISC (Reduced Instruction Set Computer) |
| Larger set of instructions. | Smaller set of instructions. |
| Simpler compiler design. | More complex compiler design. |
| Many addressing modes. | Few addressing modes, fixed instruction format. |
| Variable instruction length. | Fixed instruction length. |
| Higher clock cycles per instruction. | Low clock cycles per instruction (often one). |
| Emphasis is on hardware. | Emphasis is on software. |
| Pipelining is difficult or not possible. | Pipelining is possible, enabling faster execution. |
In essence, CISC offloads complexity to the hardware, while RISC offloads it to the software compiler, a trade-off that defined processor design for decades.
With this understanding of processor types and architectures, we can now focus on the specific implementation found in our target device: the 8051 microcontroller.