3.0 How Data and Instructions are Handled: Von Neumann vs. Harvard Architecture
The way a processor accesses data and the program instructions it needs to execute is a fundamental design choice. This choice primarily falls into two categories: the Von Neumann architecture and the Harvard architecture.
3.1 The Von Neumann Architecture: A Shared Path
The Von Neumann architecture uses a single data path or bus for both instructions and data. The core consequence of this design is that the CPU must perform its operations sequentially. It cannot fetch a new instruction from memory at the same time it is performing a read or write operation on data, as both actions require the same shared bus.
3.2 The Harvard Architecture: Separate Paths
The Harvard architecture, in contrast, offers separate storage and signal buses for instructions and data. This design allows for simultaneous access to both. The CPU can fetch the next instruction from program memory while, at the same time, accessing data from data memory.
3.3 Head-to-Head Comparison
| Von Neumann | Harvard |
| A single shared memory is used for both code and data. | Separate memories are used for code and data. |
| Requires two clock cycles to access code and data. | Can be done in a single clock cycle due to separate buses. |
| Slower in speed. | Higher speed. |
| Simple in design. | Complex in design. |
3.4 The ‘So What?’: The Impact on Performance
The key trade-off between these two architectures is simplicity versus speed. The Von Neumann architecture results in simpler hardware, as there is only one memory system to manage. However, the Harvard architecture achieves higher performance because its parallel data and instruction buses allow the processor to work more efficiently, accessing both code and data in the same clock cycle.
This leads us from how a processor gets its instructions to the nature of the instructions themselves.