The 8051’s memory map is a critical aspect of its design, featuring a strict division between program memory (ROM) and data memory (RAM). This structure directly impacts software development and system interfacing, as internal and external memory spaces have distinct characteristics and access methods.

3.2 Program Memory (ROM)

The 8051 can address up to 64K bytes of external program memory. This space is addressed by the Program Counter (PC), a 16-bit register that can hold addresses from 0000H to FFFFH. Upon system reset, the PC is initialized to 0000H. Consequently, the CPU expects to find the first program instruction at this ROM location, making it the mandatory starting point for all firmware.

3.3 Internal Data Memory (RAM)

The 8051 contains 128 bytes of internal RAM, occupying the address range from 00H to 7FH. This internal data memory is partitioned into three distinct sections:

• Register Banks: The first 32 bytes, from address 00H to 1FH, contain four banks of eight general-purpose registers (R0-R7). Only one bank is active at any time, selected via the Program Status Word (PSW) register.
• Bit-Addressable Area: This 16-byte section spans from 20H to 2FH. Each individual bit within this memory block can be directly accessed and manipulated by single-bit instructions, a feature highly useful for control applications.
• General-Purpose RAM (Scratch Pad): The 80 bytes from 30H to 7FH are available for general-purpose data storage, parameter passing, and application variables.

3.4 Stack Implementation

The stack is a section of RAM used for temporary data storage, primarily for storing return addresses during subroutine calls and for saving register values. Its operation is managed by the Stack Pointer (SP) register.

The SP is an 8-bit register, initialized to 07H on reset. This configuration causes the stack to begin at RAM location 08H, as the first PUSH operation increments the SP before storing data.

• PUSH Operation: The Stack Pointer (SP) is incremented by one, after which the operand is stored at the memory location addressed by the new SP value.
• POP Operation: The operand is retrieved from the memory location addressed by the current SP, after which the SP is decremented by one.

The data within these memory structures is accessed and manipulated by a dedicated set of CPU registers.