3.1 Historical Context and Evolution

The Intel 8051 is a foundational device in the history of embedded systems. It can be considered a pioneering “system on a chip,” an architecture that defined a generation of embedded design. Even today, its architecture remains highly relevant for learning the core concepts of microcontroller operation, memory organization, and peripheral control.

Intel’s journey began with the invention of the first microprocessor, the 4004. Following this, Intel introduced the 8-bit 8051 microcontroller in 1981. It earned the “system on a chip” moniker because it integrated all essential components onto a single piece of silicon. The original 8051 included:

• 128 bytes of RAM (Random Access Memory)
• 4K bytes of on-chip ROM (Read-Only Memory)
• Two 16-bit timers
• One serial communication port
• Four 8-bit input/output ports

The 8051 became immensely popular, and Intel licensed its architecture to other manufacturers. This led to the creation of many 8051 “flavors”—versions produced by different companies that were code-compatible but offered variations in speed and the amount of on-chip memory. This means a program written for an original Intel 8051 will run on a compatible version from another manufacturer.

3.2 The 8051 Family: Variants and Comparison

Several key variants of the 8051 were developed, each with a slightly different feature set.

• 8052: This was an enhanced version of the 8051. It included all the standard features of the 8051, plus an extra 128 bytes of RAM (for a total of 256 bytes), an extra timer (for a total of three), and 8K bytes of on-chip ROM.
• 8031: This variant is often referred to as a “ROM-less” 8051 because it has 0K bytes of on-chip ROM. To use an 8031, a designer must add external ROM containing the program to be executed. This design allows for a much larger program space—up to 64K bytes of external memory. However, this flexibility comes at a cost: in the process of adding external ROM, the 8031 loses two of its four I/O ports, which are repurposed to address the external memory.

The feature differences between these core family members are summarized below.

3.3 Core Features and Block Diagram

The standard 8051 microcontroller comes bundled with a robust set of features that made it a versatile choice for a wide range of embedded applications.

• Memory: 4KB of on-chip program memory (ROM) and 128 bytes of on-chip data memory (RAM).
• Registers: 32 general-purpose registers each of 8-bit, organized into four register banks.
• Flags: 128 user defined software flags.
• Buses: An 8-bit bidirectional data bus and a 16-bit unidirectional address bus.
• Timers: Two 16-bit timers/counters.
• Interrupts: Three internal and two external interrupt sources.
• I/O: Four 8-bit ports for input/output operations.
• Pointers: A 16-bit program counter (PC) and a 16-bit data pointer (DPTR).
• Special Features: Many variants also include features like UARTs for serial communication, Analog-to-Digital Converters (ADC), and operational amplifiers.

Conceptually, the internal block diagram of the 8051 reveals a central processing unit (CPU) connected to its various on-chip peripherals via internal buses. The CPU communicates directly with the RAM and ROM, as well as the specialized hardware for the timers, the serial port, and the four parallel I/O ports. A bus control block manages the flow of data and addresses, while an oscillator circuit provides the system clock that synchronizes all operations. This integrated layout is what defines the 8051 as a true “system on a chip.”

3.4 Registers and Memory Architecture

The 8051’s CPU manipulates data through a set of registers. Understanding their function is fundamental to programming the device.

Storage Registers

• Accumulator (Register A): This 8-bit register is central to all arithmetic and logic operations. It holds one of the operands and stores the result of most calculations.
• “R” Registers (R0-R7): These eight 8-bit registers (per bank) serve as auxiliary or temporary storage. They are essential helper registers for calculations. For example, to compute (R1 + R2) – (R3 + R4), one might first add R3 and R4, store the temporary result in R5, then add R1 and R2, and finally subtract the value in R5.
• “B” Register: This 8-bit register is similar to the Accumulator but has a specialized primary use in multiplication and division operations (MUL AB and DIV AB). When not used for these instructions, it can serve as a general-purpose temporary storage register.
• Data Pointer (DPTR): The DPTR is the only user-accessible 16-bit register in the 8051. Its primary function is to hold a 16-bit address for pointing to data stored in external memory.
• Program Counter (PC): The PC is a 16-bit register that always holds the memory address of the next instruction to be executed. Upon initialization, the PC is set to 0000h. After each instruction is executed, the PC is automatically incremented to point to the next one.
• Stack Pointer (SP): The SP is an 8-bit register that holds the address of the location from which the next value is to be removed from the stack. On initialization, the SP is set to 07h. When a value is pushed onto the stack, the SP is first incremented by 1, and the value is then stored at that new location. When a value is popped, the value is retrieved from the location pointed to by the SP, which is then decremented by 1.

Program Status Word (PSW) Register

The PSW is an 8-bit register also known as the flag register. It contains status bits that reflect the current state of the CPU after an operation.

The RS0 and RS1 bits are used to select the active register bank according to the following mapping:

3.5 Memory Space Allocation

ROM Space

The 8051’s Program Counter is 16 bits wide, which allows it to address a maximum of 64K bytes of program (opcode) memory (2^16 = 65,536). The memory space for program code always starts at address 0000H. For an 8051 with 4K of on-chip ROM, the address range would be 0000H to 0FFFH.

RAM Space

The 128 bytes of internal RAM are assigned addresses from 00H to 7FH and are organized into three distinct sections:

1. Register Banks (Addresses 00H – 1FH): The first 32 bytes are allocated for the four register banks. Each bank contains eight registers (R0-R7). The active bank is selected using the RS0 and RS1 bits in the PSW register. By default, bank 0 is active upon reset.
2. Bit-Addressable RAM (Addresses 20H – 2FH): The next 16 bytes of RAM are bit-addressable, meaning each of the 128 individual bits in this block can be directly read or written by software.
3. Scratch Pad RAM (Addresses 30H – 7FH): The remaining 80 bytes are for general-purpose read/write storage. This area is commonly used by programmers to store data and parameters during program execution.

The Stack

The stack is a section of RAM used for the temporary storage of information. It is a Last-In, First-Out (LIFO) structure.

• Access: The Stack Pointer (SP) register is used to access the stack. The SP always points to the last used location of the stack.
• PUSH Operation: When a value is “pushed” onto the stack, the SP is first incremented by 1, and the content is then saved to the new memory location indicated by the SP.
• POP Operation: When a value is “popped” from the stack, the content from the memory location pointed to by the SP is retrieved, and the SP is then decremented by 1.

This detailed hardware architecture forms the foundation upon which all software runs. We will now explore the practical methods for programming the 8051 and controlling its powerful I/O capabilities.