4.0 CPU Registers
CPU registers are high-speed storage locations within the processor used to temporarily hold data, addresses, and status information. A comprehensive understanding of each register’s specific function is essential for efficient 8051 programming.
4.2 Primary Registers
Accumulator (A): The primary 8-bit register for all arithmetic and logic operations. The results of most ALU operations are stored in the Accumulator.
B Register: An 8-bit register used in conjunction with the Accumulator for multiplication (MUL AB) and division (DIV AB) instructions. It also serves as a general-purpose temporary storage register.
‘R’ Registers (R0-R7): A set of eight 8-bit auxiliary registers organized into four selectable banks. They are used for temporary data storage and operand manipulation.
Data Pointer (DPTR): The only user-accessible 16-bit register. Its primary function is to hold a 16-bit address for accessing external data or program memory.
Program Counter (PC): A 16-bit register that holds the address of the next instruction to be fetched and executed. It is automatically incremented by the CPU after each instruction fetch.
Stack Pointer (SP): An 8-bit register that points to the top of the stack in internal RAM. It is automatically modified by instructions that use the stack, such as PUSH, POP, CALL, and RET.
4.3 Program Status Word (PSW) Register
The Program Status Word (PSW) is an 8-bit flag register that reflects the current status of the CPU and the results of arithmetic operations. Several of its bits are conditional flags that can be tested by jump instructions.
| Bit | Symbol | Function |
| PSW.7 | CY | Carry Flag. Set if there is a carry out from the D7 bit during an arithmetic operation. |
| PSW.6 | AC | Auxiliary Carry Flag. Set if there is a carry from bit D3 to D4 during an ADD or SUB operation. Used for BCD arithmetic. |
| PSW.5 | F0 | Flag 0. A general-purpose flag bit available for user definition. |
| PSW.4 | RS1 | Register Bank Select Bit 1. Used with RS0 to select the active register bank. |
| PSW.3 | RS0 | Register Bank Select Bit 0. Used with RS1 to select the active register bank. |
| PSW.2 | OV | Overflow Flag. Set if the result of a signed arithmetic operation is too large, causing an overflow into the sign bit. |
| PSW.0 | P | Parity Flag. Set or cleared by hardware during an instruction cycle to indicate whether the accumulator contains an even or odd number of set bits (1s). |
4.4 Register Bank Selection
The active register bank (R0-R7) is selected by configuring the RS1 and RS0 bits in the PSW register.
| RS1 (PSW.4) | RS0 (PSW.3) | Selected Register Bank |
| 0 | 0 | Bank 0 (Default) |
| 0 | 1 | Bank 1 |
| 1 | 0 | Bank 2 |
| 1 | 1 | Bank 3 |
This architecture of internal registers enables the 8051 to interface with the external world through its versatile I/O ports.