6.1 Understanding Timers and Counters

Timers and interrupts are critical components in real-time embedded systems. Timers provide the ability to measure time intervals and generate precise delays, which are essential for scheduling tasks and controlling periodic events. Interrupts provide an efficient mechanism for the system to react to asynchronous events from hardware or software, forming the basis for responsive and multitasking-like behavior.

• A timer is a specialized clock used for measuring time intervals or generating software delays. It is incremented by the microcontroller’s internal machine cycle clock.
• A counter is a device used for counting external events. It is incremented by a signal transition (e.g., a pulse) on an external input pin.

The key differences are summarized below:

6.2 The 8051 Timers: Registers and Configuration

The standard 8051 has two 16-bit timers: Timer 0 and Timer 1. Since the 8051 is an 8-bit architecture, each 16-bit timer is accessed as a pair of 8-bit registers.

• Timer 0 Registers: The low byte is TL0 and the high byte is TH0.
• Timer 1 Registers: The low byte is TL1 and the high byte is TH1.

TMOD (Timer Mode) Register

Both timers are configured using the 8-bit TMOD register. The lower 4 bits configure Timer 0, and the upper 4 bits configure Timer 1. The bit layout for each timer’s configuration is identical.

• GATE: When this bit is set, the timer will only run while its corresponding external interrupt pin (INT0 or INT1) is high. This allows for hardware control over the timer’s operation.
• C/T (Counter/Timer): This bit selects the operating mode.
  • C/T = 0: Timer mode. The timer is incremented by the internal machine clock.
  • C/T = 1: Counter mode. The timer is incremented by an external event on the Tx pin.
• M1, M0 (Mode Select): These two bits select one of four operating modes.

6.3 Timer Operating Modes

The 8051 timers can operate in four different modes, selected by the M1 and M0 bits in the TMOD register.

• Mode 0 (13-Bit Timer Mode): An older mode that configures the timer as a 13-bit counter.
• Mode 1 (16-Bit Timer Mode): This is the most commonly used mode. TLx and THx are cascaded to form a full 16-bit timer, allowing for counts from 0 to 65,535.
• Mode 2 (8-Bit Auto-Reload Mode): In this mode, the timer operates as an 8-bit counter (TLx). When TLx overflows (goes from 255 to 0), it is automatically reloaded with the value stored in THx. This is extremely useful for generating fixed-period events, such as the baud rate for serial communication.
• Mode 3 (Split Timer Mode): This mode applies only to Timer 0. It splits Timer 0 into two independent 8-bit timers: one using the TL0 register and the other using the TH0 register.

To initialize a timer, you must first configure the TMOD register and then set the appropriate run control bit (TR0 or TR1). For example, to configure Timer 0 in 16-bit timer mode and start it:

MOV TMOD, #01H   ; Set Timer 0 to Mode 1 (16-bit timer)

SETB TR0         ; Start Timer 0

6.4 The Interrupt System

An interrupt is a signal that indicates an event requiring immediate attention has occurred. When the CPU receives an interrupt, it suspends its current task to execute a special function called an Interrupt Service Routine (ISR).

• Hardware Interrupts are triggered by an external device, such as a sensor or a button.
• Software Interrupts are triggered by an exceptional condition (like division by zero) or a special instruction.

Interrupts vs. Polling

Polling is a technique where the microcontroller continuously monitors the status of a device to see if it needs service. This is highly inefficient, as the CPU spends all its time checking, unable to perform other tasks.

The difference can be understood with an analogy:

• Interrupts are like a shopkeeper. The shopkeeper can work on other tasks until a customer arrives (the interrupt event) and requests service. This is efficient.
• Polling is like a salesperson who goes door-to-door, constantly asking if anyone needs service. This is inefficient and time-consuming.

Interrupt Service Routine (ISR) and Vector Table

The ISR is the specific piece of code that is executed in response to an interrupt. The 8051 has a fixed area in program memory called the Interrupt Vector Table, which stores the starting addresses of the ISR for each interrupt source.

Interrupt Execution Steps

When an interrupt is triggered, the 8051 performs the following steps automatically:

1. It finishes executing the current instruction.
2. It pushes the address of the next instruction (the Program Counter) onto the stack.
3. It jumps to the corresponding address in the Interrupt Vector Table.
4. It executes the Interrupt Service Routine (ISR) found at that address.
5. The ISR must end with the RETI (Return from Interrupt) instruction, which pops the return address from the stack back into the PC, allowing the main program to resume.

6.5 Interrupt Management

Enabling and Disabling Interrupts

Upon reset, all interrupts are disabled. They must be enabled in software before the microcontroller will respond to them. This is managed by the IE (Interrupt Enable) register.

The IE is a bit-addressable register with the following structure:

• EA (IE.7): Global Interrupt Enable. If EA=0, all interrupts are disabled. If EA=1, individual interrupts can be enabled by setting their respective bits.
• ET2 (IE.5): Enable Timer 2 interrupt (in 8052 and variants).
• ES (IE.4): Enable Serial port interrupt.
• ET1 (IE.3): Enable Timer 1 interrupt.
• EX1 (IE.2): Enable External interrupt 1.
• ET0 (IE.1): Enable Timer 0 interrupt.
• EX0 (IE.0): Enable External interrupt 0.

Interrupt Priority

The 8051 allows for two levels of interrupt priority: high and low. This is configured using the IP (Interrupt Priority) register. Upon reset, all interrupts are assigned a low priority. By setting the corresponding bit in the IP register to 1, an interrupt can be elevated to high priority.

• PT1: Timer 1 Priority
• PX1: External Interrupt 1 Priority
• PT0: Timer 0 Priority
• PX0: External Interrupt 0 Priority

This priority system allows for an “interrupt inside an interrupt.” A high-priority interrupt can interrupt the ISR of a low-priority interrupt. However, an interrupt can never be interrupted by another interrupt of the same or lower priority.

With this understanding of internal peripherals, we can now turn our attention to the external tools and methodologies used to develop, debug, and finalize a complete embedded system.