The integrated peripherals of the 8051 are a defining feature of its design. Hardware blocks for timing, counting, and interrupt handling operate semi-autonomously from the CPU, enabling efficient and responsive real-time control.

8.2 Timers and Counters

8.2.1 Overview

The standard 8051 includes two 16-bit timers, Timer 0 and Timer 1. These can be configured to operate as timers for generating time delays or as event counters that increment in response to external events.

8.2.2 Associated Registers

Each 16-bit timer is composed of two 8-bit registers that are accessible by software:

• Timer 0: TH0 (high byte) and TL0 (low byte)
• Timer 1: TH1 (high byte) and TL1 (low byte)

8.2.3 TMOD Register

The TMOD (Timer Mode) register is an 8-bit register used to configure the operational mode for both timers. The lower four bits configure Timer 0, and the upper four bits configure Timer 1.

• GATE: When set, the timer only runs while its corresponding external interrupt pin (INT0/INT1) is high.
• C/T: Selects between Counter mode (1) and Timer mode (0).
• M1, M0: These two bits select the operational mode of the timer.

8.2.4 Operational Modes

The M1 and M0 bits in the TMOD register select one of four possible modes for each timer:

• Mode 0 (13-bit Timer): Operates as a 13-bit timer/counter.
• Mode 1 (16-bit Timer): A standard 16-bit timer/counter that counts from 0000H to FFFFH.
• Mode 2 (8-bit Auto-Reload): An 8-bit timer (TLx) that automatically reloads its value from THx upon overflow, ideal for generating periodic signals such as baud rates.
• Mode 3 (Split-Timer): Splits Timer 0 into two separate 8-bit timers, using TL0 and TH0 as independent timers.

8.3 Interrupt System

8.3.1 Interrupt Sources

The 8051 has six sources that can trigger an interrupt, causing the CPU to suspend its current task and execute a dedicated Interrupt Service Routine (ISR).

1. Reset: Power-on reset.
2. External Hardware Interrupt 0 (INT0): Triggered by pin P3.2.
3. Timer 0 Overflow (TF0): Triggered when Timer 0 overflows.
4. External Hardware Interrupt 1 (INT1): Triggered by pin P3.3.
5. Timer 1 Overflow (TF1): Triggered when Timer 1 overflows.
6. Serial Communication (RI/TI): Triggered when a byte is received or transmitted.

8.3.2 Interrupt Vector Table

When an interrupt occurs, the CPU jumps to a fixed address in program memory to find the start of the corresponding ISR. This mapping is defined by the Interrupt Vector Table.

8.3.3 Interrupt Enable (IE) Register

The IE (Interrupt Enable) register is used to globally or individually enable/disable the interrupt sources.

• EA (IE.7): The global enable bit. If EA is cleared, all interrupts are disabled.
• ES (IE.4): Enables the Serial Port interrupt.
• ET1 (IE.3): Enables the Timer 1 interrupt.
• EX1 (IE.2): Enables External Interrupt 1.
• ET0 (IE.1): Enables Timer 0 interrupt.
• EX0 (IE.0): Enables External Interrupt 0.

8.3.4 Interrupt Priority (IP) Register

The IP (Interrupt Priority) register configures each interrupt source to one of two priority levels: high or low. A high-priority interrupt can interrupt a low-priority interrupt service routine, but not vice-versa. The bits in the IP register that correspond to the interrupts are PX0, PT0, PX1, and PT1.

The configuration of these peripherals is managed through a set of Special Function Registers.