2.1 Overview of Design Methodologies

Once the conceptual design of a digital system is complete, engineers are faced with a critical decision: choosing the physical implementation strategy. This choice involves a fundamental trade-off between key design metrics, including performance (speed), manufacturing cost, silicon area (density), and design time. Each methodology offers a different balance of these factors, making it suitable for different applications and market needs.

The four primary design styles that an engineer can choose from are:

• Field Programmable Gate Array (FPGA)
• Gate Array (GA)
• Standard-Cell Based Design
• Full-Custom Design

We will begin our analysis with the most flexible and rapidly prototyped of these styles: the Field Programmable Gate Array.

2.2 Field Programmable Gate Array (FPGA)

A Field Programmable Gate Array (FPGA) is an integrated circuit containing a large array of logic gates—from tens of thousands to over a million—with programmable interconnections. Unlike other chip technologies that are manufactured with a fixed function, an FPGA can be programmed by the user in the “field” to perform a specific function after it has been manufactured.

A typical FPGA architecture consists of three main components:

• I/O Blocks: These are located at the periphery of the chip and serve as the interface between the internal logic and the external world.
• Configurable Logic Blocks (CLBs): These are the core functional elements distributed across the chip. Each CLB can be configured to perform a variety of logic operations, typically using lookup tables and flip-flops.
• Routing Channels and Programmable Multiplexers: A vast network of programmable interconnects, including horizontal and vertical routing channels and PSM (Programmable Multiplexers), allows the CLBs and I/O blocks to be wired together in a highly flexible manner.

The design process for an FPGA involves defining the desired functionality of the CLBs and the interconnection patterns of the PSMs using a hardware descriptive language like VHDL or Verilog. This configuration data is then loaded onto the chip to implement the final design.

Advantages and Disadvantages of FPGAs

• Advantages:
  • Short Design Time: The time from design completion to a functional chip is extremely short, as no physical manufacturing steps are required.
  • Re-programmability: The chip can be reprogrammed, which is ideal for prototyping, debugging, and applications where the hardware function may need to be updated.
• Disadvantages:
  • Higher Cost: On a per-chip basis, FPGAs are generally more expensive than other design styles, especially for high-volume production.
  • Lower Performance/Density: The programmable logic and routing overhead can lead to lower performance and less efficient use of silicon area compared to more customized solutions.

For applications requiring rapid prototyping but with different manufacturing trade-offs, the Gate Array presents another viable option.

2.3 Gate Array (GA) Design

Gate Array (GA) design, also known as mask-programmable gate array, ranks second to FPGA in terms of rapid prototyping capability. While FPGAs rely on user programming to define their function, a GA is customized through the final layers of the chip’s physical manufacturing process, specifically through the design of its metal interconnect masks.

The manufacturing process for a Gate Array is divided into two steps:

1. Phase 1 (Pre-fabrication): Wafers are fabricated with an array of uncommitted, generic transistors. These prefabricated wafers, often called “base wafers,” can be mass-produced and stockpiled.
2. Phase 2 (Customization): To implement a specific design, a custom mask is created to define the metal interconnects. This final metal layer is then patterned onto the base wafers, wiring the uncommitted transistors together to form the desired logic gates and circuits.

Because only the final metallization steps are custom, the turn-around time is significantly shorter than for a fully custom chip, typically ranging from a few days to a few weeks. Early GA platforms used dedicated routing channels between rows of transistors to simplify interconnections, with libraries of pre-defined metal patterns for basic logic gates.

A more advanced architecture is the Sea-of-Gates (SOG) design. In an SOG chip, the dedicated routing channels are removed, and the entire chip surface is covered with a continuous “sea” of uncommitted nMOS and pMOS transistors. This provides greater routing flexibility and higher potential logic density. The trade-off is that some of the uncommitted transistors must be sacrificed and used for inter-cell routing, but the overall chip utilization and speed are generally higher than that of an FPGA.

2.4 Standard-Cell Based Design

Standard-cell based design is a widely used methodology that requires a full custom mask set for fabrication. This approach, also known as polycell design, relies on a pre-designed and pre-characterized library of logic cells to construct the chip.

The core of this methodology is the standard cell library, which contains a few hundred different types of cells, including basic logic gates (inverters, NAND, NOR), more complex gates (AOI, OAI), and sequential elements like D-latches and flip-flops. Often, multiple versions of each cell are available with different drive strengths to allow designers to optimize for speed and fan-out requirements.

Each cell in the library is extensively characterized and contains a wealth of information critical for modern design tools:

• Delay time versus load capacitance characteristics
• Circuit simulation models (e.g., SPICE)
• Timing simulation models
• Fault simulation models
• Cell data for automated place-and-route tools
• Mask data for manufacturing

Physically, all cells in the library are designed with a fixed height. This allows them to be placed side-by-side in rows to form the chip’s logic. Power and ground rails are designed to run parallel to the upper and lower boundaries of the cell, enabling adjacent cells to share a common power and ground bus, which simplifies the layout process significantly.

2.5 Full-Custom Design

Full-custom design represents the pinnacle of customization, where the entire mask design for the chip is created from scratch without relying on any pre-existing cell libraries. In this style, the designer has complete control, specifying the geometry, orientation, and placement of every single transistor.

The primary advantage of this approach is the potential for maximum performance and minimum silicon area. However, it comes with significant drawbacks:

• High Development Cost: The labor-intensive nature of full-custom layout leads to very high design costs.
• Long Design Cycle: The design process is extremely time-consuming, resulting in very long development times.

The design productivity is usually very low; typically a few tens of transistors per day, per designer. Due to these factors, full-custom design is typically reserved for very high-volume products where the manufacturing cost savings can justify the initial investment, or for performance-critical circuits. Examples include memory chips (like SRAM and DRAM), where the highly regular structure allows for dense, hand-optimized cell layouts, and high-performance microprocessors. To mitigate the high costs, the concept of design reuse (re-using previously designed full-custom blocks) is becoming increasingly important.

Regardless of the design style chosen—from the programmability of an FPGA to the meticulous detail of a full-custom layout—all are ultimately built upon the same fundamental semiconductor device: the MOS transistor.