6.1 Fundamentals of Sequential Logic

In contrast to combinational circuits, where the output is solely a function of the current inputs, sequential circuits have outputs that depend on both the current inputs and the previous state of the circuit. This is because sequential circuits contain memory elements that store information about past inputs. This ability to “remember” previous states is fundamental to building registers, counters, and state machines, which are essential components of any digital system.

Sequential circuits can be broadly classified into three types:

1. Bistable Circuits: These circuits have two stable operating states. They will remain in one of these two states indefinitely until forced into the other state by an external input. Examples include latches, flip-flops, and memory cells.
2. Monostable Circuits: These circuits have only one stable state. They can be temporarily forced into a quasi-stable state, but they will eventually return to their single stable state after a certain period of time. Timers and pulse generators are common examples.
3. Astable Circuits: These circuits have no stable states. Their output continuously oscillates between several states, never settling in one. Ring oscillators are a prime example of astable circuits.

The fundamental building block of most sequential logic is the bistable circuit, most commonly realized as a latch.

6.2 Latches

SR Latch based on NOR Gate

The Set-Reset (SR) latch is one of the simplest bistable elements. When constructed from two cross-coupled NOR gates, its operation is as follows:

• Set State: An input of S=1, R=0 forces the output Q to 1 (and Q’ to 0).
• Reset State: An input of S=0, R=1 forces the output Q to 0 (and Q’ to 1).
• Hold State: An input of S=0, R=0 causes the latch to retain its current state.
• Not Allowed: The input combination S=1, R=1 is forbidden because it forces both outputs to 0, violating the complementary nature of Q and Q’.

In a CMOS implementation, two NOR gates are cross-coupled. For example, if S is high and R is low, the parallel-connected nMOS transistors in the first gate turn on, pulling Q’ low. This low value on Q’ is fed back to the second gate, keeping its pMOS transistors on and its output Q high.

SR Latch based on NAND Gate

An SR latch can also be built from cross-coupled NAND gates. This version responds to active-low inputs.

• Set State: An input of S=0, R=1 forces Q to 1.
• Reset State: An input of S=1, R=0 forces Q to 0.
• Hold State: An input of S=1, R=1 causes the latch to hold its state.
• Invalid Condition: The input S=0, R=0 is the invalid condition for a NAND-based latch.

CMOS D Latch

The D (Data) latch is designed to pass an input value D to the output Q when enabled. A common CMOS implementation uses transmission gates (TGs). The operation is controlled by a clock (CLK) signal:

• When CLK is high, the input TG is on, and the feedback TG is off. The value of D is passed directly to the output Q. The latch is “transparent.”
• When CLK is low, the input TG turns off, and the feedback TG turns on. The latch is disconnected from the D input and holds its last value in a feedback loop.

While latches are useful, many synchronous systems require more robust, edge-triggered memory elements, which leads to the concept of flip-flops.

6.3 Clocked Latches and Flip-Flops

To synchronize state changes in a digital system, memory elements are often controlled by a clock signal. A Clocked SR Latch is a basic example, where the latch is only responsive to the S and R inputs when the CLK signal is high. When CLK is low, the latch holds its current state regardless of S and R. This can be efficiently implemented in CMOS using an AND-OR-Invert (AOI) gate structure.

Clocked JK Latch

The JK latch is an enhancement of the SR latch that eliminates the indeterminate state. It uses feedback from the outputs to the inputs. Its four modes of operation are:

• Hold (J=0, K=0): The latch retains its current state.
• Set (J=1, K=0): The latch sets (Q=1) on the next active clock edge.
• Reset (J=0, K=1): The latch resets (Q=0) on the next active clock edge.
• Toggle (J=1, K=1): The output of the latch inverts its state on the next active clock edge.

Flip-Flops (SR, D, JK, T) are typically edge-triggered versions of their latch counterparts. They are designed to change their state only on the rising or falling edge of the clock signal, not while the clock level is high or low. This provides more precise control over state transitions in synchronous digital systems.

Designing these complex sequential and combinational systems by drawing individual transistors is impractical. A more abstract and powerful method is required, which is provided by Hardware Description Languages (HDLs).