3.1 Introduction to CMOS Technology

The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is the fundamental building block of virtually all modern VLSI circuits. Its invention and subsequent miniaturization have been the primary drivers of the digital revolution. Among the various MOS technologies, Complementary MOS (CMOS) has become the dominant choice for implementing today’s integrated circuits, from CPUs and memory to the processors in cell phones.

The widespread adoption of CMOS is due to a number of key advantages that make it exceptionally well-suited for large-scale digital applications:

• Low Power Dissipation: In its static state (i.e., when inputs are not changing), a CMOS logic gate consumes virtually no power.
• Relatively High Speed: CMOS devices offer excellent switching speeds, enabling high-performance computation.
• High Noise Margins: The logic levels are well-separated, providing strong immunity to electrical noise.
• Wide Operating Voltage Range: CMOS circuits can operate reliably across a broad range of supply voltages.

To appreciate how CMOS technology achieves these benefits, we must first understand the physical structure and operating principles of the individual MOSFET.

3.2 Physical Structure of a MOSFET

At its core, a MOSFET is a “sandwich” structure composed of three distinct layers built on a semiconductor substrate:

1. Metal Layer: The gate electrode, which controls the transistor’s operation.
2. Silicon Dioxide (Oxide) Layer: A very thin (typically 10 nm to 50 nm) insulating layer of SiO₂ that separates the gate from the substrate.
3. Semiconductor Layer: The silicon substrate, which forms the body of the device.

This MOS structure effectively forms a capacitor, where the gate and substrate act as the two conductive plates and the silicon dioxide layer serves as the dielectric. By applying an external voltage to the gate, we can manipulate the concentration and distribution of charge carriers within the substrate beneath the gate.

To understand this manipulation, let’s consider the electrical properties of a P-type semiconductor substrate. The concentration of charge carriers (electrons and holes) in a semiconductor is governed by the Mass Action Law:

n * p = n_i^2

Where:

• n is the concentration of free electrons.
• p is the concentration of holes.
• n_i is the intrinsic carrier concentration for the semiconductor (e.g., silicon).

In a p-type substrate doped with an acceptor concentration of N_A, the hole and electron concentrations at thermal equilibrium are given by:

• p_po = N_A (Hole concentration is approximately the acceptor concentration)
• n_po = n_i^2 / N_A (Electron concentration is very low)

The energy band diagrams of the individual MOS components reveal the physical principles at work. Key concepts include:

• Band Gap: The energy difference between the conduction and valence bands of the semiconductor (1.1 eV for silicon), which defines its fundamental electrical properties.
• Fermi Potential (Φ_Fp): The difference between the intrinsic Fermi level (the midpoint of the band gap) and the actual Fermi level of the doped semiconductor. It is a direct measure of how heavily the material is doped. The formula is Φ_Fp = (E_F – E_i) / q.
• Electron Affinity (qx): The energy required to move an electron from the bottom of the conduction band to a vacuum (free space).
• Work Function (qΦ_S): The total energy required to move an electron from the material’s Fermi level to free space. It is the sum of the electron affinity and the energy difference from the Fermi level to the conduction band: qΦ_S = (E_c – E_F) + qx. Critically, the work function of the metal gate is different from that of the p-type silicon. This difference is what causes the energy bands to bend at the silicon-oxide interface when the MOS system is formed, a phenomenon essential for creating the transistor’s channel.

By applying external voltages to this MOS structure, we can further manipulate this band bending to attract or repel charge carriers, allowing the device to function as a highly effective electronic switch.

3.3 Working Principle and Regions of Operation

A complete MOSFET device is formed by adding two n-type regions, known as the source and drain, to the basic MOS capacitor structure. These regions are placed on either side of the gate, and the area of the substrate directly beneath the gate oxide is known as the channel. The operation of the transistor is controlled by the gate-to-source voltage (V_GS).

The key to the MOSFET’s operation is the concept of the threshold voltage (V_TO). When the gate-to-source voltage V_GS is below this threshold, the channel is non-conductive. However, when V_GS exceeds V_TO, a sufficient number of mobile electrons are attracted to the surface of the p-type substrate, forming a conductive n-type “inversion layer” or channel. This channel creates a conducting path between the source and the drain, allowing current to flow when a drain-to-source voltage (V_DS) is applied.

The behavior of this drain current (I_D) is characterized by different regions of operation, primarily determined by the magnitude of V_DS:

1. Linear Region: For a small positive V_DS, the channel acts like a resistor, and the resulting drain current I_D is directly proportional to V_DS.
2. Edge of Saturation: As V_DS increases, the voltage drop across the channel becomes significant. At the drain end, the effective gate-to-channel voltage decreases, causing the channel to become narrower. When V_DS reaches a specific value known as the saturation voltage (V_DSAT), the channel depth and mobile charge at the drain end are reduced to nearly zero. This condition is called “pinch-off.”
3. Saturation Region: For any V_DS > V_DSAT, a depleted region forms near the drain. The pinch-off point moves slightly toward the source, and the drain current I_D becomes largely independent of V_DS, saturating at a nearly constant value. The electrons entering this depletion region from the channel are swept to the drain by the high electric field.

To model the device’s behavior and use it in circuit design, it is necessary to derive the mathematical relationship between its terminal voltages and the resulting drain current.

3.4 MOSFET Current-Voltage (I-V) Characteristics

Deriving the precise I-V characteristics of a MOSFET requires solving complex three-dimensional electrostatic problems. However, a highly effective and widely used simplifying assumption known as the Gradual Channel Approximation (GCA) allows us to derive an accurate model. GCA assumes that the electric field in the direction of current flow (along the channel) is much smaller than the field perpendicular to the channel (from the gate).

To set up the analysis, we consider an n-channel MOSFET with its source and substrate grounded (V_S = V_B = 0) and a gate voltage V_GS > V_TO, ensuring a conductive channel exists. Let V_C(y) be the channel voltage at a distance y from the source terminal.

The derivation proceeds by considering an infinitesimally small segment of the channel and then integrating its properties over the full channel length:

1. The total mobile electron charge per unit area in the inversion layer at point y is a function of the local channel voltage V_C(y): Q1(y) = -C_ox * [V_GS – V_C(y) – V_TO] where C_ox is the gate oxide capacitance per unit area.
2. This charge concentration determines the incremental resistance dR of a small channel segment of length dy: dR = -dy / (W * μ_n * Q1(y)) where W is the channel width and μ_n is the electron surface mobility.
3. The constant drain current I_D flowing through this incremental resistance creates a differential voltage drop dV_c: dV_c = I_D * dR
4. By substituting the expressions for dR and Q1(y), we can relate the differential voltage drop to the drain current. To find the total relationship for the entire transistor, we must sum up these infinitesimal effects. This is accomplished by integrating the equation along the channel length from y = 0 (source) to y = L (drain), corresponding to a channel voltage change from V_C = 0 to V_C = V_DS.

This derivation yields the following key I-V equations for the n-channel MOSFET:

• Linear Region (V_DS < V_GS – V_TO): I_D = (μ_n * C_ox / 2) * (W / L) * [2 * (V_GS – V_TO) * V_DS – V_DS^2]
• Saturation Region (V_DS ≥ V_GS – V_TO): I_D = (μ_n * C_ox / 2) * (W / L) * (V_GS – V_TO)^2

With a solid understanding of the fundamental transistor, we can now analyze its application in the most basic and essential digital logic circuit: the inverter.