4.1 Principle of Operation

The inverter is the nucleus of all digital designs. It is the simplest possible logic gate, and a thorough understanding of its operational properties is essential for designing more complex structures like NAND gates, adders, and even entire microprocessors. The electrical behavior of these larger circuits can be largely extrapolated from the characteristics of the fundamental inverter.

The ideal inverter performs a simple Boolean NOT operation. A high input voltage, representing logic ‘1’ (typically Vdd), results in a low output voltage, representing logic ‘0’ (typically 0V), and vice versa. The transition between these states occurs at a theoretical inverter threshold voltage, Vth, which for an ideal inverter is Vdd / 2.

A generalized circuit structure for an nMOS-based inverter consists of a “driver” transistor and a “load” element connected between the power supply Vdd and the output node. The inverter’s input voltage (V_in) is applied to the gate of the nMOS driver transistor, making V_in equivalent to the transistor’s gate-to-source voltage (V_GS). The inverter’s output voltage (V_out) is taken from the drain of the driver, making V_out equivalent to its drain-to-source voltage (V_DS). Practical inverters are built using different types of load devices, which significantly affect their performance. The first type we will examine is the simple resistive load inverter.

4.2 Resistive Load Inverter

The resistive load inverter uses an enhancement-type nMOS transistor as the driver and a simple linear resistor, R_L, as the load element.

The circuit operates as follows:

• When V_in is low (V_in < V_TH): The nMOS driver transistor is in the cutoff region and does not conduct any current. Since no current flows through the load resistor R_L, there is no voltage drop across it. Consequently, the output voltage V_out is pulled up to the supply voltage, V_DD.
• As V_in increases above V_TH: The driver transistor turns on and initially enters the saturation region. It begins to conduct current, which flows through R_L, causing V_out to decrease. As V_in continues to increase, the driver transistor eventually moves into the linear region, and V_out continues to fall towards 0V.

The relationship between the input and output voltage is captured by the Voltage Transfer Characteristic (VTC) curve. This curve clearly shows the operating modes of the driver transistor as the input voltage sweeps from low to high. While simple, resistive loads suffer from a significant limitation: a linear resistor occupies a very large silicon area, making this implementation impractical for dense integrated circuits. A more area-efficient solution is to use another MOSFET as an active load device.

4.3 Inverters with N-type MOSFET Load

Using an n-type MOSFET as an active load device offers the primary advantage of consuming significantly less silicon area compared to a passive resistor. There are two main configurations for an enhancement-type nMOS load inverter:

1. Saturated Enhancement Load: In this configuration, the load transistor is biased to operate in its saturation region. It requires only a single voltage supply, but its output high voltage (V_OH) is limited to V_DD – V_T (where V_T is the threshold voltage of the load transistor), which reduces noise margins.
2. Linear Enhancement Load: Here, the load is biased to always operate in its linear region. This allows the output high level V_OH to reach the full supply voltage V_DD. However, this configuration has the major disadvantage of requiring two separate power supplies, making it impractical for most designs.

Both of these enhancement load inverter types suffer from relatively high static power dissipation, making them unsuitable for large-scale digital applications. A significant improvement was the Depletion Load nMOS Inverter. This design uses an nMOS transistor with a negative threshold voltage (a depletion-type device) as the load. Its advantages include a sharp VTC transition, better noise margins, the use of a single power supply, and a smaller layout area. With its gate connected to its source (V_GS,load = 0), the depletion load device is always on.

Despite these improvements, the industry largely transitioned away from all-nMOS logic to a more power-efficient and robust design: the CMOS inverter.

4.4 The CMOS Inverter

The Complementary MOS (CMOS) inverter is the most popular and important inverter configuration used in modern VLSI design. Its widespread adoption is due to its superior performance, particularly its extremely low power consumption.

The CMOS inverter circuit is distinguished by its use of a complementary pair of transistors: an nMOS transistor and a pMOS transistor. The input signal is connected to the gates of both transistors. The nMOS transistor (the “pull-down” device) is connected between the output and ground, while the pMOS transistor (the “pull-up” device) is connected between the output and the power supply, V_DD.

The operation of the CMOS inverter is elegantly simple and efficient:

• Low Input (V_in < V_TO,n): When the input is logic ‘0’, the nMOS transistor is OFF (in cutoff). Simultaneously, the pMOS transistor is turned ON (operating in its linear region). The conducting pMOS transistor creates a low-resistance path from V_DD to the output node, pulling V_out up to a strong logic ‘1’ level (V_OH = V_DD).
• High Input (V_in > V_DD + V_TO,p): When the input is logic ‘1’, the pMOS transistor is OFF (in cutoff). The nMOS transistor is turned ON (operating in its linear region). The conducting nMOS transistor creates a low-resistance path from the output node to ground, pulling V_out down to a strong logic ‘0’ level (V_OL = 0).

Crucially, in either of these steady states (input high or input low), one of the transistors is always off. This means there is no direct current path from V_DD to ground, resulting in near-zero static power dissipation. Power is only consumed during the brief moments when the inverter is switching states.

The VTC of the CMOS inverter can be divided into five distinct regions, with the operating modes of the nMOS and pMOS transistors summarized in the table below:

The superior characteristics of the CMOS inverter—full rail-to-rail output swing, high noise margins, and negligible static power—make it the preferred building block for all modern combinational logic circuits.