5.1 Principles of Combinational Logic

Combinational logic circuits are digital gates that perform Boolean operations on multiple input variables. Their defining characteristic is that the outputs are determined solely by the current state of the inputs; they have no memory of past states. Any combinational logic circuit can be represented as a multiple-input, single-output system that maps a set of input Boolean values to an output Boolean value.

In the positive logic convention used in digital design, a high voltage (V_DD) represents the Boolean value ‘1’, and a low voltage (0V or Ground) represents the Boolean value ‘0’. Using the principles of CMOS design, we can construct fundamental gates like NOR and NAND, which are functionally complete and can be used to build any combinational logic function.

5.2 CMOS NOR and NAND Gates

CMOS Two-Input NOR Gate

The CMOS NOR gate implements the function Z = NOT (A OR B). Its circuit structure consists of two main parts:

• n-net (Pull-down): Composed of two parallel-connected nMOS transistors.
• p-net (Pull-up): Composed of two series-connected pMOS transistors. This p-net is the complementary dual of the n-net.

Operation: If either input A or input B (or both) is high (logic ‘1’), at least one of the parallel nMOS transistors will turn on, creating a conducting path that pulls the output node down to ground (logic ‘0’). In this state, the series-connected p-net is cut off. Only when both inputs are low (logic ‘0’) will both nMOS transistors be off, breaking the path to ground. Simultaneously, both series pMOS transistors will turn on, creating a path that pulls the output up to V_DD (logic ‘1’). Like the CMOS inverter, no direct DC path exists between V_DD and ground in any steady state.

The switching threshold voltage for the 2-input NOR gate is given by the equation: V_th(NOR2) = (V_T,n + 0.5 * sqrt(k_p/k_n) * (V_DD – |V_T,p|)) / (1 + 0.5 * sqrt(k_p/k_n))

CMOS Two-Input NAND Gate

The CMOS NAND gate implements Z = NOT (A AND B) and its structure is the exact dual of the NOR gate:

• n-net (Pull-down): Composed of two series-connected nMOS transistors.
• p-net (Pull-up): Composed of two parallel-connected pMOS transistors.

Operation: The output will be pulled low only if both inputs A and B are high, which turns on both series nMOS transistors to create a path to ground. For any other input combination, at least one of the nMOS transistors will be off, breaking the path to ground. In these cases, at least one of the parallel pMOS transistors will be on, pulling the output high to V_DD.

The switching threshold voltage for the 2-input NAND gate is given by: V_th(NAND2) = (V_T,n + 2 * sqrt(k_p/k_n) * (V_DD – |V_T,p|)) / (1 + 2 * sqrt(k_p/k_n))

Sample layouts for these gates often feature single polysilicon lines for inputs that run vertically across both the nMOS and pMOS active regions, with horizontal metal lines for power and output bussing. A stick diagram is a useful abstraction for planning the layout topology without specifying exact dimensions. These principles of series and parallel transistor networks can be extended to create much more complex logic gates.

5.3 Complex Logic Gates

A key advantage of MOS logic is the ability to realize complex Boolean functions efficiently with a relatively small number of transistors, often within a single logic stage.

nMOS Depletion-Load Complex Logic Gate

Consider the Boolean function Z = NOT(P(S + T) + QR). An nMOS depletion-load gate can realize this function with a single load transistor and a pull-down network of driver transistors. The structure of the pull-down network directly mirrors the Boolean expression:

• The OR operation (S + T) is implemented with two parallel transistors.
• The AND operation (P AND (S+T)) is implemented by placing a transistor for P in series with the parallel S and T combination.
• The QR term is a separate series branch.
• The final OR operation between the two main terms is implemented by connecting these two branches in parallel.

Complex CMOS Logic Gates

Complex CMOS gates follow a similar principle but require the construction of a complementary pull-up network. The design principles are:

1. Design the n-net (pull-down network): The n-net is designed using the same logic as the nMOS gate: parallel-connected transistors for OR operations and series-connected transistors for AND operations.
2. Design the p-net (pull-up network): The p-net must be the dual of the n-net. The principle of duality dictates that any parallel connection in the n-net corresponds to a series connection in the p-net, and any series connection in the n-net corresponds to a parallel connection in the p-net.

The Euler Graph Method for Layout Optimization

For complex gates, the physical ordering of the input transistors can have a significant impact on the layout area. A non-optimal ordering can lead to breaks in the diffusion regions, requiring extra space. The Euler Graph Method is a technique used to find an optimal ordering.

An Euler path is an uninterrupted path that traverses every edge (transistor) in a graph exactly once. The goal is to find an identical ordering of inputs (an Euler path) for both the pull-up and pull-down networks. If such a path exists, the polysilicon gate lines for the inputs can be aligned in a single, unbroken line across both the n-net and p-net, resulting in a much more compact and area-efficient layout.

While these combinational circuits form the computational core of digital systems, they lack the ability to store information. For that, digital systems require memory elements, which are implemented using sequential logic circuits.