This section details the practical application of transistor theory, demonstrating how nMOS and pMOS transistors are configured to create the fundamental logic gates that serve as the basis for all digital computation.

5.1 The CMOS Inverter: The Nucleus of Digital Design

The inverter is the most fundamental logic gate in digital design. A clear understanding of its operation is crucial, as the electrical behavior of more complex circuits can be extrapolated from its properties. The static CMOS inverter is the most popular implementation due to its superior performance characteristics.

The principle of operation for a static CMOS inverter relies on its complementary structure, which consists of one pMOS transistor and one nMOS transistor. The pMOS acts as a “pull-up” network to the power supply (VDD), while the nMOS acts as a “pull-down” network to ground (GND). They work in opposition: when a high input is applied, the nMOS turns ON and the pMOS turns OFF, pulling the output low. When a low input is applied, the pMOS turns ON and the nMOS turns OFF, pulling the output high. This complementary pull-up/pull-down structure is the key to achieving the low static power dissipation that makes CMOS the dominant technology, as a direct path from VDD to ground never exists in a steady state.

Voltage Transfer Characteristic (VTC)

The VTC describes the output voltage as a function of the input voltage. For a CMOS inverter, this curve is divided into five distinct regions, each corresponding to a different operational state for the transistors. Key voltage points on this curve include VIL (maximum input voltage recognized as a logic low), VIH (minimum input voltage recognized as a logic high), and Vth (the switching threshold voltage where Vin = Vout).

5.2 Combinational Logic Circuits

Combinational logic circuits are gates whose outputs are Boolean functions that depend solely on the current values of the input variables. They have no memory of past inputs.

CMOS Two-Input NOR Gate

The CMOS NOR gate consists of a parallel-connected pull-down network (the “n-net”) and a series-connected pull-up network (the “p-net”). If either input A or B is high, at least one of the parallel nMOS transistors turns ON, pulling the output low. Simultaneously, the corresponding series pMOS transistor is OFF, breaking the path to VDD. Only when both inputs are low are both nMOS transistors OFF and both series pMOS transistors ON, pulling the output high.

CMOS Two-Input NAND Gate

The structure of a CMOS NAND gate is the dual of the NOR gate. It uses a series-connected n-net and a parallel-connected p-net. The output is pulled low only when both inputs A and B are high, turning ON both series nMOS transistors. If either input is low, the nMOS path to ground is broken, and at least one of the parallel pMOS transistors turns ON, pulling the output high.

General Design Principles

These examples illustrate the general principles for designing complex CMOS logic gates:

• OR operations are performed by parallel-connected driver transistors.
• AND operations are performed by series-connected driver transistors.
• The pMOS pull-up network must be the dual of the nMOS pull-down network. A series connection in one corresponds to a parallel connection in the other, ensuring the complementary operation of the gate.

5.3 Sequential Logic Circuits

In contrast to combinational circuits, the output of a sequential circuit depends on both the current inputs and the previous state of the inputs. This is achieved through the use of memory elements that store information.

NOR-based SR Latch

The SR Latch is a fundamental bistable memory element. Based on two cross-coupled NOR gates, it has two inputs, Set (S) and Reset (R), and two complementary outputs, Q and Q’.

• Set: When S=1 and R=0, the output Q is forced to 1.
• Reset: When S=0 and R=1, the output Q is forced to 0.
• Hold: When S=0 and R=0, the latch retains its previous state.
• Not Allowed: When S=1 and R=1, both outputs are forced to 0, which is an invalid, indeterminate state.

Clocked JK Latch

The Clocked JK Latch resolves the “not allowed” state of the SR latch by using feedback from the outputs to the inputs. This allows for all four input combinations to have a defined behavior. The latch is responsive to the J and K inputs only when the clock signal is high.

• Hold: When J=0 and K=0, the latch holds its current state.
• Set: When J=1 and K=0, the output Q is set to 1.
• Reset: When J=0 and K=1, the output Q is reset to 0.
• Toggle: When J=1 and K=1, the output toggles to the opposite of its current state.

These fundamental circuit implementations provide the foundation for understanding the higher level of abstraction offered by Hardware Description Languages.