Glossary of Key Terms
Glossary of Key Terms
| Term | Definition |
| Architecture (VHDL) | Describes a VHDL entity using structural, dataflow, behavioral, or mixed style. |
| Behavioral Modeling | A modeling style where the behavior of an entity is described as a set of statements executed sequentially in a specified order. |
| Blocking Assignments (Verilog) | A procedural assignment that must be executed before the execution of the statements that follow it in a sequential block. |
| CLB (Configurable Logic Blocks) | A component of an FPGA that performs the logic operation given to the module. |
| CMOS (Complementary MOSFET) | A technology widely used to form circuits, utilizing complementary nMOS and pMOS transistors. It offers low power dissipation and relatively high speed. |
| Combinational logic circuits | Circuits that perform Boolean operations on multiple input variables, where the outputs are determined as Boolean functions of the current inputs only. |
| Data Flow Modeling | A modeling style where the flow of data through an entity is expressed using concurrent (parallel) signal assignments. |
| Design Hierarchy* | The principle of “Divide and Conquer,” which involves dividing a design task into smaller tasks until it reaches its simplest level to ease manufacturing. |
| Entity Declaration (VHDL) | Defines the names, input/output signals, and modes of a hardware module. |
| FPGA (Field Programmable Gate Array) | An integrated circuit containing ten thousand to more than a million logic gates with programmable interconnections available for designers to perform given functions. |
| Full Custom Design | A design style where the entire mask design is made new without using any library, and the designer controls the geometry, orientation, and placement of every transistor. |
| Gajski-Kuhn Y-chart | A model that captures the considerations in designing semiconductor devices, with three domains (behavioral, structural, physical) on radial axes. |
| Gate Array (GA) | A design style where an array of uncommitted transistors is customized by defining the metal interconnects between them in a two-step manufacturing process. |
| Gate-level netlist | A description of a circuit in terms of gates and the connections between them. |
| Gradual Channel Approximation (GCA) | An approximation method used to simplify the three-dimensional analysis of a MOS system for deriving current-voltage characteristics. |
| Integrated circuit (IC) | A circuit created by combining thousands of transistors into a single chip. |
| Microprocessor | A VLSI device. |
| Module (Verilog) | The principal design entity in Verilog, which indicates the name and port list of a design block. |
| MOSFET | Metal-Oxide-Semiconductor Field Effect Transistor. A type of transistor formed as a sandwich of a semiconductor layer, a silicon dioxide layer, and a metal layer. |
| Nonblocking (RTL) Assignments (Verilog) | A procedural assignment that allows scheduling of assignments without blocking the procedural flow, enabling several register assignments within the same time step. |
| Physical layout | The final geometric representation of a circuit, which is verified and then sent for fabrication. |
| Procedural Assignments (Verilog) | Assignments used for updating reg, integer, time, and memory variables under the control of procedural flow constructs. |
| Register (reg – Verilog) | A data object in Verilog that holds a value from one procedural assignment to the next, used within functions and procedural blocks. |
| RTL (Register-Transfer Level) description | A design description done using HDLs that is simulated to test functionality. In Verilog, it specifies circuit characteristics using operations and data transfers between registers. |
| Semiconductor | A material, typically a slice from a single crystal of silicon, that forms one of the layers of a MOSFET. |
| Sequential circuits | Logic circuits where the output depends not only on the latest inputs but also on the condition of earlier inputs, as they contain memory elements. |
| Standard Cell Based Design | A design approach where all commonly used logic cells are developed, characterized, and stored in a standard cell library for use in a full custom mask set. |
| Structural Modeling | A modeling style where an entity is described as a set of interconnected components. |
| Transistor | A semiconductor device used to amplify or switch electronic signals and electrical power. Thousands are combined on a single chip in VLSI. |
| Verilog | A Hardware Description Language (HDL) used for describing a digital system, such as a microprocessor or a memory, at various levels of abstraction. |
| VHDL | Very high-speed integrated circuit hardware description language. A programming language used to model a digital system by dataflow, behavioral, and structural styles. |
| VLSI (Very-large-scale integration) | The process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. |
| Wire (Verilog) | A Verilog data type used to represent a physical wire in a circuit, connecting gates or modules. It cannot store a value and must be driven by a continuous assignment. |