This section outlines the core, step-by-step process for applying controlled ESD stress to a Device Under Test (DUT). Careful execution of these steps, particularly regarding sample handling, test conditions, and the selection of pin combinations, is essential for achieving an accurate and repeatable ESD classification.

6.1 Pre-Test Device Preparation and Conditions

All DUTs must meet the following conditions before any ESD stress is applied:

• Devices must have completed all normal manufacturing operations.
• A comprehensive set of DC parametric and functional tests must be performed on each device at room temperature.
• If applicable, high-temperature testing as specified by the device data sheet must also be completed.
• The ESD stress application itself shall be performed at room temperature.

6.2 Test Execution: Stress Application

The following procedure shall be used to apply ESD stress to the DUTs.

1. Use a sample size of 3 devices for the initial characterization.
2. Begin testing at the lowest voltage level specified in Table 1 (e.g., 100 V or 200 V).
3. For each pin combination specified in section 6.3, apply one positive pulse and one negative pulse.
4. Ensure a minimum interval of 1 second between consecutive pulses.
5. After stressing all required pin combinations at a given voltage level, perform a full post-test evaluation on all 3 devices (as described in section 6.4).
6. If all 3 devices pass the post-test evaluation, the same sample of 3 devices may be used for testing at the next higher voltage level. Alternatively, a fresh sample of 3 devices may be used for each new voltage level.

6.3 Pin Combination Configurations

Applying stress to a comprehensive set of pin combinations is critical for evaluating all potential ESD failure paths within the microcircuit. The following configurations, derived from Table 2 (see Appendix B), must be tested to ensure thorough device characterization.

• Configurations 1-3 (I/O pins to Power/Ground pins): These test configurations stress each non-power pin (Pin Under Test, or PUT) relative to a specific power supply or ground rail (e.g., VCC1, VSS, VDD2). This simulates an ESD event occurring on an I/O pin while the device is referenced to a particular power domain, a common failure mode.
• Configuration 4 (I/O pins to other I/O pins): This configuration stresses a non-supply pin relative to all other non-supply pins. This simulates an ESD event between two I/O pins, which is a critical test case for components on unconnected boards or during handling.

6.4 Post-Test Evaluation

After the full ESD stress routine is completed at a given voltage level, the DUTs must undergo the same comprehensive DC parametric and functional testing that was performed during the pre-test preparation phase.

The results of this post-test evaluation are used directly to determine if a device has failed, which provides the basis for its final ESD sensitivity classification.