Electrostatic Discharge Sensitivity Testing Machine Model

Glossary of Key Terms

Glossary of Key Terms

Term / Acronym	Definition
DUT	Device Under Test. The microcircuit or component being subjected to the ESD test.
EIA	Electronic Industries Association. An organization involved in developing standards for the electronics industry.
ESD	Electrostatic Discharge. The phenomenon of a sudden flow of electricity between two electrically charged objects, which this test method simulates.
I100	Current at 100 ns for 500 Ohm. A waveform specification parameter measuring the current in amperes at 100 nanoseconds into a 500 ohm load.
IEC	International Electrotechnical Commission. A worldwide organization for standardization in the electrical and electronic fields.
Ipr	Positive Ipeak for 500 Ohm. A waveform specification parameter representing the maximum positive peak current in amperes when discharging into a 500 ohm load.
Ipsl	Positive Ipeak for Short. A waveform specification parameter representing the maximum positive peak current in amperes when discharging through a shorting wire.
JEDEC	JEDEC Solid State Technology Association. A standard-setting body for the microelectronics industry, which submitted the PAS that became IEC/PAS 62180.
MM	Machine Model. A specific model of ESD testing that simulates a discharge from a machine or piece of metal equipment, characterized by a 200 pF capacitor and negligible series resistance.
PAS	Publicly Available Specification. A technical specification, not fulfilling all requirements for a standard, made available by an organization. IEC-PAS 62180 may be investigated for transformation into a full International Standard.
PUT	Pin Under Test. The specific pin on the DUT that is currently being connected to the ESD pulse source (Terminal A).
tfr	Resonance Frequency for Short. A waveform specification parameter in MHz, representing the frequency of the ringing observed in the current waveform during a discharge through a shorting wire.
Worst-case pin	The pin socket combination that has the shortest or longest wiring path from the pulse generating circuit to the test socket. It is used for waveform verification to ensure compliance under extreme parasitic conditions.