2.0 Detailed Analysis of Frame Structures by Hierarchical Level
2.1 Interface at 1544 kbit/s
The 1544 kbit/s interface, commonly associated with T1 circuits, represents a foundational structure in digital telephony. The strategic importance of this hierarchical level lies in its flexible multiframe options, which allow network operators to choose between enhanced error monitoring with a data link or dedicated channel-associated signalling within the same low-bandwidth stream. This adaptability has made it a long-standing and versatile component of digital networks.
Frame and Multiframe Characteristics
The basic frame is composed of 193 bits (numbered 1 to 193) and repeats at a rate of 8000 Hz. The first bit of every frame is designated as the F-bit. This single bit is multifunctional, serving as the primary mechanism for frame alignment, performance monitoring, and providing a dedicated data link for operational messages. Two distinct multiframe methods define how the F-bit is used across a sequence of frames.
Method 1: 24-Frame Multiframe
This method prioritizes performance monitoring and data transport. The F-bits across a 24-frame multiframe are allocated to three main functions:
- Multiframe Alignment Signal (FAS): A specific six-bit pattern (001011) is used to identify the multiframe boundary.
- Cyclic Redundancy Check (CRC-6): For error monitoring, a CRC-6 procedure is implemented. The six check bits, designated e₁ to e₆, are transmitted in the F-bit position of frames 2, 6, 10, 14, 18, and 22 of the multiframe.
- Data Link (DL): The remaining F-bits, designated as ‘m’ bits, are used to create a 4 kbit/s data link for transmitting maintenance or operational messages.
Method 2: 12-Frame Multiframe
In contrast to the 24-frame structure, this method is designed specifically to support channel-associated signalling. The F-bit alternates between providing a frame alignment signal and a multiframe alignment signal (S-bit), as detailed in Table 3/G.704 of the recommendation. This structure forgoes the CRC-6 and data link capabilities in favor of dedicating bandwidth for signalling.
Signalling Capabilities
The 1544 kbit/s interface supports two primary signalling methods. Common channel signalling uses a full 64 kbit/s channel for signalling information. Alternatively, channel-associated signalling can be implemented using the 12-frame multiframe structure, where bits in frames 6 and 12 are “robbed” from user channels to create independent signalling channels (A and B).
This foundational structure provides a clear contrast to the higher-capacity 6312 kbit/s level, which aggregates multiple primary rate signals.
2.2 Interface at 6312 kbit/s
The 6312 kbit/s interface serves as a second-order multiplexing level, designed to combine multiple primary rate signals into a single, higher-capacity stream. Its frame structure reflects this role by adopting a more consolidated approach to overhead, grouping all service bits at the end of the frame for alignment, error monitoring, and alarms, which differs significantly from the single F-bit approach of the 1544 kbit/s level.
Frame Structure and Overhead
The basic frame at this level consists of 789 bits and repeats at a rate of 8000 Hz. The final five bits of the frame (bits 785 to 789) are reserved as F-bits. These five bits are collectively used for frame alignment, performance monitoring, and providing a data link.
Alignment, Error Checking, and Data Link
A four-frame multiframe structure is used to organize the overhead functions within the F-bits.
- Alignment Signal: The frame and multiframe alignment signal is a nine-bit pattern (110010100) carried on the F-bits across frames 1 and 2, specifically excluding bit 789 of frame 1.
- Cyclic Redundancy Check (CRC-5): Performance monitoring is achieved using a CRC-5 mechanism. The five check bits (e₁ to e₅) occupy the five F-bit positions (bits 785-789) of frame 4.
- Data Link and Alarms: The overhead bits also include a data link bit (‘m’) providing a 4 kbit/s channel, and a remote end alarm indication bit (‘a’) to signal a loss of frame alignment condition to the far end.
The design of the 6312 kbit/s interface is tailored for its multiplexing function, leading to a different architectural philosophy than that of the widely adopted 2048 kbit/s structure used internationally.
2.3 Interface at 2048 kbit/s
The 2048 kbit/s interface, widely known as E1, is a cornerstone of international telecommunications, particularly outside of North America. Its design philosophy differs markedly from the T1-based hierarchy by dedicating an entire timeslot to signalling and another to framing and maintenance. This clear separation of functions, along with an optional and more robust CRC mechanism, provides enhanced operational capabilities.
Frame Structure and Alignment
The E1 frame is 256 bits long, divided into 32 timeslots of 8 bits each, and repeats at an 8000 Hz rate. The first timeslot (TS0) is reserved for overhead.
- Frame Alignment Signal (FAS): In alternate frames, bits 2 through 8 of TS0 contain the Frame Alignment Signal (0011011).
- Non-FAS Overhead: In frames that do not contain the FAS, TS0 is used for other functions. This includes a remote alarm indication bit (‘A’) and several spare bits (Sₐ) that can be used for national applications or, more commonly, as a message-based data link for conveying Synchronization Status Messages (SSM).
CRC-4 Procedure
An optional but powerful Cyclic Redundancy Check (CRC-4) procedure can be enabled to provide superior error monitoring. This procedure organizes 16 frames into a multiframe, which is further divided into two 8-frame Sub-Multiframes (SMF I and SMF II).
- CRC Multiframe Alignment: Bit 1 of the TS0 non-FAS frames is used to carry the CRC multiframe alignment signal (001011).
- CRC and Error Bits: Bit 1 of the TS0 FAS frames is used to transmit the four CRC-4 check bits (C₁ to C₄) across the multiframe. Two additional bits (E bits) are used to signal CRC error events detected in the corresponding received SMF.
Synchronization Status and Signalling
The spare bits (Sₐ) in TS0 of non-FAS frames can be used to transmit Synchronization Status Messages (SSM), which are critical for maintaining timing and preventing slips in a synchronous network. Furthermore, channel time slot 16 (TS16) is reserved exclusively for signalling, which can be configured for either common channel signalling or channel-associated signalling that uses its own 16-frame multiframe structure.
The dedicated and structured approach of the 2048 kbit/s interface contrasts with the higher-order 8448 kbit/s interface, which multiplexes these signals.
2.4 Interface at 8448 kbit/s
The 8448 kbit/s interface represents a third hierarchical level in the E1-based digital hierarchy, designed to multiplex four independent 2048 kbit/s signals. The frame structure at this level introduces a distinct method for framing, distributing the alignment signal across two separate parts of the frame, and dedicates specific bits for service functions rather than grouping them into a single timeslot.
Frame Structure and Alignment
The frame at this level is 1056 bits long and has a repetition rate of 8000 Hz. The frame alignment signal is a 14-bit pattern (11100110 100000) that is uniquely split. The first eight bits are located in positions 1 to 8, and the remaining six bits are located in positions 529 to 534 of the frame.
Service Digits and Error Monitoring
Two dedicated bits are reserved for service and maintenance functions:
- Bit 535: This bit is used for alarm indication to the remote end.
- Bit 536: This bit is reserved for national use.
Unlike the lower-level interfaces that embed a CRC in the primary framing overhead, the G.704 recommendation for 8448 kbit/s specifies a CRC-6 procedure applied to a specific 64 kbit/s channel time slot (slot 99). This provides end-to-end performance monitoring for that particular channel link rather than for the entire 8448 kbit/s aggregate signal.
This structure leads into the even higher-capacity 44 736 kbit/s transport level, which employs a far more complex approach to overhead management.
2.5 Interface at 44 736 kbit/s
The 44 736 kbit/s interface is a high-capacity transport level within the digital hierarchy. Its architecture is defined by a sophisticated multiframe structure that moves beyond simple alignment and error checking. The design dedicates a rich set of overhead bits to enable extensive operations, administration, and maintenance (OAM) functions, reflecting its role as a critical transport backbone.
Multiframe Structure
The fundamental unit at this level is a multiframe containing 4760 bits. This multiframe is partitioned into seven M-subframes, each containing 680 bits. Each M-subframe is further divided into eight blocks, where each block consists of one overhead bit followed by 84 payload bits. This intricate subdivision allows for the distribution of 56 overhead bits throughout the multiframe.
Overhead Bit Functions
The 56 overhead bits per multiframe are systematically allocated to perform a variety of essential OAM tasks:
- Alignment: A two-level alignment system ensures robust synchronization.
- M-bits (M1, M2, M3): These three bits form the multiframe alignment signal (010).
- F-bits (F1, F2, F3, F4): These four bits form the M-subframe alignment signal (1001).
- Error Monitoring: Two distinct mechanisms provide performance visibility.
- P-bits (P1, P2): These two bits provide local performance monitoring by carrying parity information calculated over the 4704 payload bits of the preceding multiframe.
- X-bits (X1, X2): These bits serve as a reporting mechanism to the remote end, used to indicate that errored multiframes have been detected.
- Path Maintenance (C-bits): The 21 C-bits offer significant versatility. They can be used for bulk data transport or for enhanced applications. A key application is C-bit Parity, which enables the use of a Far-End Alarm and Control (FEAC) channel. This channel is used to send alarm status codes (e.g., loss of signal, equipment failure) and control codewords (e.g., initiate loopbacks) from the near-end terminal to the far-end terminal.
The comprehensive overhead of the 44 736 kbit/s interface provides a powerful toolkit for network management, which can be clearly contrasted with the simpler structures of the lower hierarchical levels.