The 1544 kbit/s interface, commonly known as the T1 or DS1 rate, is a foundational element in digital telephony and data networks, with widespread deployment, particularly in North America and Japan. Its frame structure provides a standardized method for multiplexing 24 individual channels into a single high-speed digital stream.

The basic frame characteristics are defined as follows: the frame length is 193 bits, numbered sequentially from 1 to 193. The frame repetition rate is 8000 Hz, which aligns with the sampling rate for standard voice channels.

The first bit of each frame is designated as the F-bit. This overhead bit serves multiple critical purposes, including frame alignment to ensure the receiving equipment can correctly identify the start of each frame, performance monitoring via error detection mechanisms, and the provision of a dedicated data link for operational communication.

2.1 24-Frame Multiframe Structure (Method 1)

The primary method for allocating the F-bit’s functions is based on a 24-frame multiframe structure. This approach organizes 24 consecutive frames into a larger logical unit, allowing the F-bit in each frame to be assigned a specific role within the multiframe context.

Table 1: Multiframe Structure for the 24-frame Multiframe at 1544 kbit/s

The F-bit assignments detailed in the table serve the following functions:

• Frame Alignment Signal (FAS): The F-bit of every fourth frame (4, 8, 12, 16, 20, 24) is used to form the multiframe alignment signal. This signal consists of the repeating pattern 001011, which allows the receiving terminal to identify where each 24-frame multiframe begins.
• Data Link (DL): The F-bit of every other frame (1, 3, 5, etc.), designated as ‘m’ bits, provides a 4 kbit/s data link for operations and maintenance messages.
• Cyclic Redundancy Check (CRC): The F-bit of frames 2, 6, 10, 14, 18, and 22, designated as e₁ to e₆, carries a 6-bit CRC checksum for error monitoring.

2.1.1 Cyclic Redundancy Check (CRC-6) Procedure

The CRC-6 is a method of performance monitoring where six check bits (e₁ to e₆) are calculated over a block of data and transmitted within the F-bit positions of frames 2, 6, 10, 14, 18, and 22.

The CRC-6 Message Block (CMB) is the sequence of 4632 bits over which the checksum is calculated. It begins at bit position 1 of a multiframe (N) and ends at bit position 4632 of that same multiframe. This block is treated as the coefficients of a polynomial, which is then divided by a generator polynomial.

The generator polynomial for the check-bit sequence is: x⁶ + x + 1.

The resulting 6-bit remainder from the division process forms the CRC-6 check bits, which are inserted into the next multiframe. At the receiving end, the same calculation is performed and the result is compared to the received check bits to detect transmission errors.

2.1.2 4 kbit/s Data Link and Performance Reporting

The 4 kbit/s data link utilizes the ‘m’ bits within the F-bit positions to transmit operations and maintenance messages. These messages are typically 16-bit sequences, which can be designated for priority communications (such as alarms) or other operational tasks.

Table 2: Assigned Operations Data Link Messages

Performance verification is based on the calculation of CRC checksums and tracking other events at the receiving terminal. This information is formatted into a 15-octet performance report message and transmitted back to the sending terminal via the data link once per second.

1. Octet 1 (Flag): 01111110. Marks the beginning of the message frame.
2. Octet 2 (SAPI/C/R/EA): Contains the Service Access Point Identifier (00111000 or 00111010), Command/Response bit, and Extended Address bit.
3. Octet 3 (TEI/EA): Contains the Terminal Endpoint Identifier (00000001) and Extended Address bit.
4. Octet 4 (Control): Set to 00000011 for unacknowledged information transfer.
5. Octets 5-13 (Information Field): This field contains four consecutive one-second performance reports (t₀, t₀-1, t₀-2, t₀-3), with t₀ being the most recent. The structure of a single one-second report is a 12-bit field containing the following information:
   • G1 (CRC Error Count): A count of CRC error events (1 to ≥319).
   • G2 (Payload Loopback Activated): A flag indicating active loopback.
   • G3-G6 (Reserved/Other Events): Includes flags for Severely-Errored Framing Events, Frame Alignment Bit Error Events, Line Code Violations, and Slip Events.
   • FE (Far End Block Error): Shall be set to 0.
   • U1, U2 (Under Study): For synchronization use.
   • Nm, Nn (Reserved): Set to 0.
6. Octet 14 (FCS): Frame Check Sequence (variable).
7. Octet 15 (Flag): 01111110. Marks the end of the message frame.

2.2 12-Frame Multiframe Structure (Method 2)

An alternative 12-frame multiframe structure exists for the 1544 kbit/s interface. This method provides a simpler allocation of the F-bit for frame alignment, multiframe alignment, and signalling.

Table 3: F-bit Allocation for the 12-Frame Multiframe

2.3 Channelized Interface Characteristics

The primary payload of the 1544 kbit/s frame is designed to carry multiple channels.

For carrying twenty-four 64 kbit/s channels, bits 2 to 193 of the frame are structured to carry 24 octet-interleaved time slots. Each time slot consists of 8 bits, corresponding to a single 64 kbit/s channel.

For carrying forty-eight 32 kbit/s channels, bits 2 to 193 of the frame are structured to carry 48 four-bit interleaved time slots. The 1544 kbit/s frame is structured into four independent 384 kbit/s 12-channel time slot groupings. The signalling for these channels is managed using a dedicated multiframe structure.

Table 4: 32 kbit/s Channel Time Slots Frame Structure for 1544 kbit/s Interface

Table 5: 32 kbit/s Signalling Grouping Channel Multiframe Structure

The next section will detail the frame structure for the second hierarchical level, the 6312 kbit/s interface.