7.1 Annex A: CRC Implementation Examples

This annex provides functional descriptions of shift-register based hardware implementations for the CRC procedures specified in the main body of this document. The following descriptions are based on the circuit diagrams provided in the source recommendation; diagrams are not rendered here.

• 1544 kbit/s interface (CRC-6) The implementation uses a 6-stage shift register. The generator polynomial is x⁶ + x + 1. The input, which is the 4632-bit CRC Message Block (CMB), is fed serially into the circuit. When the last bit of the CMB has been processed, the six CRC bits (e₁ to e₆) are available at the outputs of the shift register stages. The outputs are reset to 0 after each CMB.
• 6312 kbit/s interface (CRC-5) This implementation is based on a 5-stage shift register. The generator polynomial is x⁵ + x⁴ + x² + 1. The input CMB is fed serially into the circuit. When the last bit of the CMB (bit number 784 of frame number 4) has been processed, the five CRC bits (e₁ to e₅) are available at the outputs. The outputs are reset to 0 after each CMB.
• 2048 kbit/s interface (CRC-4) The implementation for the CRC-4 procedure uses a 4-stage shift register. The generator polynomial is x⁴ + x + 1. The input to the shift register is the Sub-Multiframe (SMF), with the initial C-bit values set to 0. The SMF is fed serially into the circuit starting with bit 1. When the last bit of the SMF has been processed, the four CRC bits (C₁ to C₄) are available at the outputs and are transmitted in the next SMF. The outputs are reset to 0 after each SMF.

7.2 Annex B: List of Abbreviations

The following table defines the abbreviations used throughout this specification.