4.0 Frame Structure Specification at 2048 kbit/s
The 2048 kbit/s interface, commonly known as E1, is the primary rate standard used in most parts of the world outside of North America and Japan. It is a cornerstone of the Plesiochronous Digital Hierarchy (PDH) and forms the basis for carrying voice, data, and signalling information in a wide range of telecommunications networks.
The basic frame characteristics are defined as a frame length of 256 bits, numbered 1 to 256, with a frame repetition rate of 8000 Hz. The 256 bits are typically divided into 32 time slots of 8 bits each. The first time slot (Time Slot 0) is reserved for framing and synchronization purposes.
Table 7: Allocation of Bits 1 to 8 of the Frame (Time Slot 0)
| Bit number | ||||||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | |
| Alternate frames | Sᵢ | \multicolumn{7}{c | }{Frame alignment signal} | |||||
| Frame containing the frame alignment signal | (Note 1) | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
| Frame not containing the frame alignment signal | (Note 1) | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ |
| (Note 2) | (Note 3) | \multicolumn{5}{c | }{(Note 4)} | |||||
| NOTE 1 – Sᵢ = Bits reserved for international use. One specific use is described in 2.3.3. Other possible uses may be defined at a later stage. If no use is realized, these bits should be fixed at 1 on digital paths crossing an international border. | ||||||||
| NOTE 2 – The bit is fixed at 1 to assist in avoiding simulations of the frame alignment signal. | ||||||||
| NOTE 3 – A = Remote alarm indication. In undisturbed operation, set to 0; in an alarm condition, set to 1. | ||||||||
| NOTE 4 – Sₐ₄ to Sₐ₈ = Additional spare bits whose use may be as follows: for specific point-to-point applications, as a message-based data link, for national usage, or for synchronization interface messages. Bits Sₐ₄ to Sₐ₈ (where these are not used) should be set to 1 on links crossing an international border. |
4.1 CRC-4 Multiframe Procedure
To provide enhanced error monitoring and protection against false frame alignment, a Cyclic Redundancy Check (CRC-4) procedure is defined. This procedure organizes frames into a 16-frame multiframe, which is numbered from 0 to 15. The multiframe is further divided into two 8-frame Sub-Multiframes (SMF I, frames 0-7, and SMF II, frames 8-15).
Table 8: CRC-4 Multiframe Structure
| Sub-Multiframe (SMF) | Frame number | Bits 1 to 8 of the frame | |||||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
| 0 | C₁ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| 1 | 0 | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ | |
| 2 | C₂ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| I | 3 | 0 | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ |
| 4 | C₃ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| 5 | 1 | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ | |
| 6 | C₄ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| 7 | 0 | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ | |
| 8 | C₁ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| 9 | 1 | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ | |
| 10 | C₂ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| II | 11 | 1 | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ |
| 12 | C₃ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| 13 | E | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ | |
| 14 | C₄ | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
| 15 | E | 1 | A | Sₐ₄ | Sₐ₅ | Sₐ₆ | Sₐ₇ | Sₐ₈ | |
| NOTE 1 – E = CRC-4 error indication bits. | |||||||||
| NOTE 2 – Sₐ₄ to Sₐ₈ = Spare bits (see Note 4 to Table 7). | |||||||||
| NOTE 3 – C₁ to C₄ = Cyclic Redundancy Check 4 (CRC-4) bits. | |||||||||
| NOTE 4 – A = Remote alarm indication (see Table 7). |
The CRC-4 multiframe alignment signal is 001011. This signal is transmitted in bit 1 of Time Slot 0 in frames that do not contain the frame alignment signal.
The CRC-4 calculation procedure is performed on each 2048-bit Sub-Multiframe.
- The generator polynomial is x⁴ + x + 1.
- Multiplication/Division: A CRC-4 word, located in sub-multiframe N, is the remainder after the multiplication of the polynomial corresponding to sub-multiframe N-1 by x⁴ and division by the generator polynomial.
- Encoding: The CRC-4 bits in the SMF are initially replaced by binary 0s. The SMF is then acted upon by the division process, and the resulting remainder is stored and inserted into the respective CRC-4 bit locations of the next SMF.
- Decoding: A received SMF is acted upon by the division process after its CRC-4 bits have been extracted and replaced by 0s. The resulting remainder is compared to the CRC-4 bits received in the next SMF. If they match, the checked SMF is assumed to be error-free.
4.2 Synchronization Status Messages (SSM)
The S-bits (Sa4 to Sa8) in Time Slot 0 of frames not containing the frame alignment signal are used to convey Synchronization Status Messages (SSMs). These messages indicate the quality level of the synchronization source from which the signal is timed, which is critical for maintaining network-wide timing stability.
Table 9: Synchronization Status Message (SSM) Bit Allocation
| QL | Sₐn1 Sₐn2 Sₐn3 Sₐn4 (Note 1) | Synchronization Quality Level (QL) description |
| 0 | 0000 | Quality unknown (existing synchronization network) |
| 1 | 0001 | Reserved |
| 2 | 0010 | Rec. G.811 |
| 3 | 0011 | Reserved |
| 4 | 0100 | SSU-A (Note 2) |
| 5 | 0101 | Reserved |
| 6 | 0110 | Reserved |
| 7 | 0111 | Reserved |
| 8 | 1000 | SSU-B (Note 2) |
| 9 | 1001 | Reserved |
| 10 | 1010 | Reserved |
| 11 | 1011 | Synchronous Equipment Timing Source (SETS) |
| 12 | 1100 | Reserved |
| 13 | 1101 | Reserved |
| 14 | 1110 | Reserved |
| 15 | 1111 | Do not use for synchronization |
| NOTE 1 – n = 4, 5, 6, 7 or 8 (i.e. one Sₐ bit only) depending on operator selection. | ||
| NOTE 2 – In a previous version of this Recommendation, the terms “G.812 transit” and “G.812 local” were used. These terms were changed to Synchronization Supply Unit (SSU), respectively type A and type B, to align with the clock definitions in Recommendation G.812. |
4.3 Channelized Interface Characteristics
The 2048 kbit/s frame is designed to carry thirty-two 64 kbit/s channels. Bits 1 to 256 of the frame accommodate 32 octet-interleaved time slots, numbered 0 to 31. Time Slot 0 is used for framing and synchronization, while time slots 1-15 and 17-31 are available for user data.
Time Slot 16 is typically reserved for signalling information associated with the user channels. When used for channel-associated signalling, its 64 kbit/s capacity is sub-multiplexed across the 16-frame multiframe to provide four signalling bits (a, b, c, d) for each of the 30 user channels.
Table 10: Bit Allocation of Channel Associated 64 kbit/s Signalling
| Time Slot 16 of frame 0 | Time Slot 16 of frame 1 | Time Slot 16 of frame 2 | — | Time Slot 16 of frame 15 | |
| Bit allocation | 0000xyxx | abcd channel 1 | abcd channel 2 | — | abcd channel 15 |
| abcd channel 16 | abcd channel 17 | — | abcd channel 30 | ||
| NOTE 1 – Channel numbers refer to telephone channel numbers. 64 kbit/s channel time slots 1 to 15 and 17 to 31 are assigned to telephone channels numbered 1 to 30. | |||||
| NOTE 2 – This bit allocation provides four 500 bit/s signalling channels designated a, b, c, and d for each channel for telephone and other services. | |||||
| NOTE 3 – When bits b, c, or d are not used they should have the values: b = 1, c = 0, d = 1. | |||||
| NOTE 4 – x = Spare bit, to be set to 1 if not used. | |||||
| NOTE 5 – y = Bit used for alarm indication to the remote end. In undisturbed operation, set to 0; in an alarm condition, set to 1. |
The specification next examines the 8448 kbit/s interface.